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XCR3032XL 32 Macrocell CPLD
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification
Features
* * * * * Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in small footprint packages - 48-ball CS BGA (36 user I/O pins) - 44-pin VQFP (36 user I/O) - 44-pin PLCC (36 user I/O) Optimized for 3.3V systems - Ultra-low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero PowerTM (FZP) CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3032XL TotalCMOS CPLD (data taken with two resetable up/down, 16-bit counters at 3.3V, 25C).
20
*
*
Typical ICC (mA)
15
10
* * * * * *
5
0 0 20 40 60 80 100 120 140 160 180 200
Frequency (MHz)
DS023_01_080101
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25C Table 1: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) Typical ICC (mA) 0 0.02 1 0.13 5 0.54 10 1.06 20 2.09 50 5.2 100 10.26 200 20.3
(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH(2) Parameter Output High voltage Test Conditions VCC = 3.0V to 3.6V, IOH = -8 mA VCC = 2.7V to 3.0V, IOH = -8 mA IOH = -500 A VOL IIL(4) IIH(4) ICCSB ICC CIN CCLK CI/O Output Low voltage Input leakage current I/O High-Z leakage current Standby current Dynamic current(5,6) Input pin capacitance(7) Clock input capacitance(7) I/O pin capacitance (7) IOL = 8 mA VIN = GND or VCC VIN = GND or VCC VCC = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz Min. 2.4 2.0(3) 90% VCC -10 -10 Max. 0.4 10 10 100 0.25 7.5 8 12 10 Unit V V V V A A A mA mA pF pF pF
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. Typical leakage current is less than 1 A. 5. See Table 1, Figure 1 for typical values. 6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 7. Typical values, not tested.
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
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DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-5 Symbol TPD1 TPD2 TCO TSUF TSU1 TSU2 TH(4) TWLH(4) TPLH(4) TR TL
(4) (4) (4) (4) (4)
-7 Max. 4.5 5.0 3.5 Min. 3.0 4.3 4.8 0 3.0 5.0 Max. 7.0 7.5 5.0 20 20 119 30 30 9.3 9.3 8.3 9.3 Min. 3.0 5.4 6.3 0 4.0 6.0 -
-10 Max. 9.1 10.0 6.5 20 20 95 30 30 11.2 11.2 10.7 11.2 Unit ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time (fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
Min.
2.5 3.0 3.5 0 2.5 4.0 -
20 20 200 30 30 7.2 7.2 5.5 6.5
fSYSTEM TINIT(4) TPOE(4) TPOD(4) TPCO(4) TPAO (4)
TCONFIG
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 3 mA at 3.6V. 6. Output CL = 5 pF.
DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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Internal Timing Parameters(1,2)
-5 Symbol Buffer Delays TIN TFIN TGCK TOUT TEN Input buffer delay Fast Input buffer delay Global Clock buffer delay Output buffer delay Output buffer enable/disable delay 0.7 2.2 0.7 1.8 4.5 1.6 3.0 1.0 2.7 5.0 2.2 3.1 1.3 3.6 5.7 ns ns ns ns ns Parameter Min. Max. Min. -7 Max. Min. -10 Max. Unit
Internal Register and Combinatorial Delays TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI1 TLOGI2 Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Internal logic delay (single p-term) Internal logic delay (PLA OR term) 1.0 0.3 2.0 3.0 1.3 1.0 2.0 3.5 2.0 2.5 1.0 0.5 2.5 4.5 1.6 1.3 2.3 5.0 2.7 3.2 1.2 0.7 3.0 5.5 2.0 1.6 2.1 6.0 3.3 4.2 ns ns ns ns ns ns ns ns ns ns
Feedback Delays TF ZIA delay 0.5 2.9 3.5 ns
Time Adders TLOGI3 TUDA TSLEW Fold-back NAND delay Universal delay Slew rate limited delay 2.0 1.2 4.0 2.5 2.0 5.0 3.0 2.5 6.0 ns ns ns
Notes: 1. These parameters guaranteed by design and characterization, not testing. 2. See XPLA3 family data sheet (DS012) for timing model.
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DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
S2
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV.
DS023_03_102401
Figure 3: AC Load Circuit
4.5
+3.0V 90%
4.0
10% 0V
TPD (ns)
TR
3.5
TL
1.5 ns
1.5 ns
3.0
1
2
4
8
16
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS023_06_042800
Outputs
DS023_05_061101
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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Pin Descriptions
Table 2: XCR3032XL User I/O Pins PC44 Total User I/O Pins 36 VQ44 36 CS48 36
Table 3: XCR3032XL I/O Pins Function Block 2 2
Notes: 1. JTAG pins
Macrocell 15 16
PC44 25 24
VQ44 19 18
CS48 G5 F4
Table 3: XCR3032XL I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC44 4 5 6 7(1) 8 9 11 12 13(1) 14 16 17 18 19 20 21 41 40 39 38(1) 37 36 34 33 32(1) 31 29 28 27 26 VQ44 42 43 44 1(1) 2 3 5 6 7(1) 8 10 11 12 13 14 15 35 34 33 32(1) 31 30 28 27 26(1) 25 23 22 21 20 CS48 A2 A1 C4 B1(1) C2 C1 D3 D1 D2(1) E1 F1 G1 E4 F2 G2 F3 C5 A6 B6 B7(1) D4 C6 D6 D7 E5(1) E7 F7 G7 G6 F5
Table 4: XCR3032XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN VCC GND No Connects PC44 2 1 44 43 32 7 38 13 10(1) 3, 15, 23, 35 22, 30, 42 VQ44 40 39 38 37 26 1 32 7 4(1) 9, 17, 29, 41 16, 24, 36 CS48 A3 B4 A4 B5 E5 B1 B7 D2 C3(1) B3, C7, E2, G4 A5, E3, E6 A7, B2, F6, G3
Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation.
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DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
Ordering Information
Example:
Device Type Speed Grade
XCR3032XL -5 VQ 44 C
Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -10 -7 -5 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay 5 ns pin-to-pin delay PC44 VQ44 CS48 Package 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Very Thin Quad Flat Pack (VQFP) 48-ball Chip Scale Package Temperature C = Commercial I = Industrial TA = 0C to +70C VCC = 3.0V to 3.6V TA = -40C to +85C VCC = 2.7V to 3.6V
Component Availability
Pins Type Code XCR3032XL -5 -7 -10 44 Plastic PLCC PC44 C C,I C, I 44 Plastic VQFP VQ44 C C,I C, I 48 Plastic BGA CS48 C C,I C, I
DS023 (v1.5) January 8, 2002 Preliminary Product Specification
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Revision History
The following table shows the revision history for this document. Date 11/18/00 02/05/01 04/11/01 Version 1.0 1.1 1.2 Initial Xilinx release. Removed Timing Model. Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers, Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Updated Typical I/V curve, Figure 2: added voltage levels. Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial packages. Added 200 MHz to Figure 1 and Table 1. changed -5 FSYSTEM to 200 MHz, -5 TF to 0.5 ns. Updated THI spec to correct a typo. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement.Updated note 5 in AC Characteristics table lowering typical current draw during configuration. Revision
04/19/01 08/27/01
1.3 1.4
01/08/02
1.5
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DS023 (v1.5) January 8, 2002 Preliminary Product Specification

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